The present invention relates to programmable logic device (PLD) configuration.
PLDs are integrated circuit devices with a variety of functional blocks that may be connected together in various ways in order to use the PLD appropriately in a wide variety of different applications. Some examples of the functional blocks are memories, processors, digital signal processors (DSPs), phase-locked loops (PLLs), logic elements (LEs), logic array blocks (LABs), etc. The functional blocks are connected via an interconnect. The PLD may be configured to use selected ones of the functional blocks in a selected way for a particular application. One way to configure the PLD is to use “configuration bits”. Configuration bits are used to configure the PLD. Some examples of configurations that may be performed are to program the interconnects, to enable certain functions in the logic elements (LEs), etc.
Some concerns arise regarding “unused” or “blank” configuration bits. Such blank configuration bits are not used to configure the PLD, but are still stored in the configuration device (an external memory used to download the configuration bits into the PLD). The blank configuration bits are stored in the configuration device so that the PLD can be configured by just shifting in the configuration bits frame by frame. One concern is that as the PLD gets bigger, the number of configuration bits increases. This also increases the number of blank configuration bits. Such blank configuration bits take up space in the memory of the configuration device. Such blank configuration bits also take time to program into the PLD.
There is a need for a configuration device that has an increased available memory size as compared to a configuration device that must store blank configuration bits. There is a need for a configuration device that does not waste time programming blank configuration bits into a PLD.
The present invention is directed toward improving these and other issues regarding configuration devices for PLDs.